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1 isl21440 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. micropower voltage reference with comparator isl21440 the isl21440 is a micropower, fga? reference and comparator on a single chip. drawing less than 1.8a supply current over the full operating temperature range, the isl21440 operates from a single 2v to 11v supply and can also be used with split bipolar supplies. the isl21440?s on-board reference provides a 1.182v 0.5% output. it features programmable hysteresis and ttl/cmos compatible outputs that sink and source current. low bias currents permit high value divider resistors for typical circuit current drains of <2.5a. the low supply current makes the isl21440 ideal for battery powered devices in battery level or low voltage monitors circuits. the isl21440 is a pin-compatible, performance upgrade of both the ltc1440, ltc1540, max921 and max931. features ? 1.8a supply current over full temperature range ? wide supply range. . . . . . . . . . . . . . . 2v to 11v ? precision 1.182v 0.5% voltage reference ? comparator with user programmable hysteresis ? temperature range . . . . . . . . . -40c to +125c ? 8 ld msop and 8 ld tdfn packages ? pin compatible upgrade to max921 and ltc1440 applications* (see page 13) ? low battery detector ?low voltage reset ? overvoltage monitor ? window comparator typical application reference voltage vs temperature v+ out in- hyst gnd v- ref in+ isl21440 - + vbat vdd 2.4m 20k lobat- 2.4m 1.8m low battery detector 1.172 1.174 1.176 1.178 1.180 1.182 1.184 1.186 1.188 1.190 -40 -20 0 20 40 60 80 100 120 temperature (c) v ref (v) v+ = 5v v+ = 2v v+ = 3v march 2, 2010 fn6532.1
2 fn6532.1 march 2, 2010 block diagram pin configuration isl21440 (8 ld msop, 8 ld tdfn) top view v+ out in- hyst gnd v- ref in+ isl21440 - + gnd out 1 2 3 4 ref hyst 8 7 6 5 in+ v+ in- v- pin descriptions pin symbol description 1 gnd ground pin. sets the comparator output low level. 2 v- negative supply input for voltage reference and comparator. 3 in+ comparator non-inverting input pin. range: v- to v+ -1.5v. 4 in- comparator inverting input pin. range: v- to v+ -1.5v 5hystcomparator hysteres is input. accepts a voltage divided from the reference output. range is vref - 50mv to vref. connect direct ly to vref for zero hysteresis. 6 ref reference output. source 2ma and sink 10a. 7 v+ positive supply input for comparator and reference. range is 2.0v to 11.0v 8 out comparator output, cmos push-pull. output swing referenced to v+ and gnd. isl21440
3 fn6532.1 march 2, 2010 ordering information part number (notes 2, 3) part marking v dd range (v) temp range (c) package (pb-free) pkg. dwg. # ISL21440IUZ 1440z 2 to 11 -40 to +125 8 ld msop m8.118 ISL21440IUZ-t13 (note 1) 1440z 2 to 11 -40 to +125 8 ld msop m8.118 isl21440irtz 1440 2 to 11 -40 to +125 8 ld tdfn l8.3x3g isl21440irtz-t13 (note 1) 1440 2 to 11 -40 to +125 8 ld tdfn l8.3x3g notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device in formation page for isl21440 . for more information on msl please see techbrief tb363 . isl21440
4 fn6532.1 march 2, 2010 table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . 2 absolute maximum ratings . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . 5 environmental operating cond itions . . . . . . . . 5 recommended operating cond itions . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . 5 typical performance curves . . . . . . . . . . . . . . . 7 functional description . . . . . . . . . . . . . . . . . . 11 device power . . . . . . . . . . . . . . . . . . . . . . . . 11 comparator section . . . . . . . . . . . . . . . . . . . . 11 voltage reference section . . . . . . . . . . . . . . . 11 applications information . . . . . . . . . . . . . . . . 11 handling and board mounting . . . . . . . . . . . . . 11 hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . 11 board assembly considerations . . . . . . . . . . . . 12 special applications considerations . . . . . . . . . 12 typical applications . . . . . . . . . . . . . . . . . . . . 12 low battery detector . . . . . . . . . . . . . . . . . . . 12 window comparator . . . . . . . . . . . . . . . . . . . 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 13 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 m8.118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 l8.3x3g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 isl21440
5 fn6532.1 march 2, 2010 absolute maximum ratings thermal information supply voltage range, v+ to gnd . . . . . . . . . -0.5v to +12v in+, in- with respect to v- . . . . . . . . -0.3v to (v+) +0.3v gnd with respect to v-. . . . . . . . . . . . . . . . . 6.0v to -0.3v v+ with respect to v- . . . . . . . . . . . . . . . . . . . 12v to -0.3v ref, hyst with respect to v-. . . . . . . . . . . . . -0.3v to 1.5v out with respect to gnd. . . . . . . . . . . (v+) +0.3v to -0.3v voltage on all other pins . . . . . . . . . . . .-0.3v to v cc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . 4000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . 350v charged device model . . . . . . . . . . . . . . . . . . . . . 2000v latch up (tested per jesd-78b; class1, level a) . . . . 100ma environmental operating conditions x-ray exposure (note 4). . . . . . . . . . . . . . . . . . . .10mrem thermal resistance (typical) ja (c/w) jc (c/w) 8 ld msop package (notes 5, 7). . . . 154 55 8 ld tdfn package (notes 5, 6) . . . . 68 8 maximum junction temperature (plastic package). . . +150c storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile (note 8) . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions temperature. . . . . . . . . . . . . . . . . . . . . . -40c to +125c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. measured with no filtering, distance of 10? from source, in tensity set to 55kv and 70ma curre nt, 30s duration. other exposure levels should be analyzed for output voltage drif t effects. see ?applications information? on page 11. 5. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center. 8. post-reflow drift for the isl21440 device voltage reference output will range from 100mv to 1.0mv based on experimental results with devices on fr4 do uble sided boards. the design engineer must take this into account when considering the reference voltage after assembly. analog specifications v+= +5.0v. v- = gnd = 0v unless otherwise specified, t a = +25c. boldface limits apply over the operating temperat ure range, -40c to +125c. symbol parameter test conditions min (note 10) typ (note 9) max (note 10) units power supply v + supply voltage range v- = gnd 2.0 11.0 v i cc supply current in+ = in- +80mv, hyst = ref 0.46 0.75 a 0.85 a comparator v os input offset voltage v cm = 2.5v msop package 3 mv 3.25 mv tdfn package 3.6 mv 3.75 mv i in input leakage current (in+, in-, hyst) v in+ = v in- = 2.5v msop package 0.1 1.4 na tdfn package 0.1 1.5 na 3 na v cm common-mode input range v- (v+) - 1.5 v cmrr common-mode rejection ratio v- to (v+ - 1.5v) msop package 1.2 3 mv/v 3.5 mv/v tdfn package 1.2 4.5 mv/v 5 mv/v isl21440
6 fn6532.1 march 2, 2010 psrr power supply rejection ratio v+ = 2v to 11v msop package 0.25 1.1 mv/v 1.2 mv/v tdfn package 0.25 1.5 mv/v 1.6 mv/v v hyst hysteresis input voltage ref - 50mv ref v t phl propagation delay - high to low transition c l = 100pf overdrive = 10mv 100 s overdrive = 100mv 50 s t plh propagation delay - low to high transition c l = 100pf overdrive = 10mv 200 s overdrive = 100mv 100 s v oh output high voltage i o = -10ma (v+) - 0.4 v v ol output low voltage i o = 3ma gnd + 0.4 v reference v ref reference voltage no load 1.176 1.188 v v ref output load regulation 0 i source 2ma -0.5 -2.0 mv -2.5 mv 0 i sink 10a 0.1 2.0 mv 2.5 mv v+ = 3.0v, v- = gnd = 0v i cc supply current in+ = in- +80mv, hyst =ref 0.40 0.7 a 0.8 a comparator v os input offset voltage v cm = 1.5v msop package 2.3 3.4 mv 3.5 mv tdfn package 2.3 4.2 mv 4.3 mv i in input leakage current (in+, in-, hyst) v in+ = v in- = 1.5v 0.1 1.1 na 3 na v cm common-mode input range v- (v+) - 1.5 v cmrr common-mode rejection ratio v- to (v+ - 1.5v) msop package 1.2 5 mv/v 5.5 mv/v tdfn package 1.2 7.5 mv/v 8 mv/v psrr power supply rejection ratio v+ = 2v to 11v msop package 0.25 1.1 mv/v 1.2 mv/v tdfn package 0.25 1.5 mv/v 1.6 mv/v v hyst hysteresis input voltage ref - 50mv ref v analog specifications v+= +5.0v. v- = gnd = 0v unless otherwise specified, t a = +25c. boldface limits apply over the operating temperat ure range, -40c to +125c. (continued) symbol parameter test conditions min (note 10) typ (note 9) max (note 10) units isl21440
7 fn6532.1 march 2, 2010 t phl propagation delay - high to low transition c l = 100pf overdrive = 10mv 100 s overdrive = 100mv 50 s t plh propagation delay - low to high transition c l = 100pf overdrive = 10mv 200 s overdrive = 100mv 100 s v oh output high voltage i o = -7ma (v+) - 0.4 v v ol output low voltage i o = 3ma gnd + 0.4 v reference v ref reference voltage no load 1.176 1.188 v v ref output load regulation 0 i source 2ma -0.5 -2.0 mv -2.5 mv 0 i sink 10a 0.1 2.0 mv -2.5 mv notes: 9. over the specified temperature range. temperature coefficient is measured by the box method whereby the change in v out is divided by the temperature range; in this case, -40c to +125c = +165c. 10. parts are 100% tested at +25c and +85c. the -40c and + 125c temperature limits are established by characterization and are not production tested. analog specifications v+= +5.0v. v- = gnd = 0v unless otherwise specified, t a = +25c. boldface limits apply over the operating temperat ure range, -40c to +125c. (continued) symbol parameter test conditions min (note 10) typ (note 9) max (note 10) units typical performance curves figure 1. i dd vs temperature figure 2. i dd vs v dd 0.40 0.41 0.42 0.43 0.44 0.45 0.46 0.47 0.48 0.49 -40 -20 0 20 40 60 80 100 120 temperature (c) i dd (a) v+ = 5v v+ = 3v 0 0.2 0.4 0.6 0.8 1.0 1.2 2 7 10 11 v dd (v) i dd (a) 3456 89 isl21440
8 fn6532.1 march 2, 2010 figure 3. v ref vs temperature figure 4. v ref vs supply voltage figure 5. v ref vs load (source) figure 6. v ref vs load (sink) figure 7. dropout - v ref output figure 8. comparator output low voltage vs load typical performance curves (continued) 1.172 1.174 1.176 1.178 1.180 1.182 1.184 1.186 1.188 1.190 -40 -20 0 20 40 60 80 100 120 temperature (c) v ref (v) v+ = 5v v+ = 2v v+ = 3v 1.172 1.174 1.176 1.178 1.180 1.182 1.184 1.186 1.188 1.190 v dd (v) 23456789101112 v ref (v) 1.175 1.176 1.177 1.178 1.179 1.180 1.181 1.182 1.183 0 0.5 1.0 1.5 2.0 2.5 3.0 load (ma) v ref (v) v+ = 2v v+ = 3v v+ = 5v 1.182 1.183 1.184 1.185 1.186 1.187 1.188 0 0.05 0.10 0.15 0.20 0.25 0 .30 0.35 0.40 0.45 0.50 load (ma) v ref (v) 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.00 1.25 1.50 1.75 2. 00 2.25 2.50 2.75 3.0 0 v dd (v) v ref (v) no load 100ma load 10ma load 0 0.5 1.0 1.5 2.0 2.5 3.0 02468101214 i load (ma) output (v) v+ = 2v v+ = 3v v+ = 5v v+ = 11v isl21440
9 fn6532.1 march 2, 2010 figure 9. comparator output high voltage vs load figure 10. hysteresis - 0mv (v+ = 5v ) figure 11. hysteresis - 12.5mv (v+ = 5v) figure 12. hysteresis - 25mv (v+ = 5v) figure 13. hysteresis - 37.5mv (v+ = 5v) figure 14. hysteresis - 50mv (v+ = 5v) typical performance curves (continued) 0 2 4 6 8 10 12 0 5 10 15 20 25 30 35 40 45 50 i load (ma) output (v) v+ = 2v v+ = 3v v+ = 5v v+ = 11v 0 1 2 3 4 5 6 -60-55-50-45-40-35-30-25-20-15-10-5 0 5 1015202530354045505560 in+ - in- (mv) output (v) 0 1 2 3 4 5 6 -60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 in+ - in- (mv) output (v) 0 1 2 3 4 5 6 -60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 in+ - in- (mv) output (v) 0 1 2 3 4 5 6 -60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 in+ - in- (mv) output (v) 0 1 2 3 4 5 6 -60-55-50-45-40-35-30-25-20-15-10-5 0 5 1015202530354045505560 in+ - in- (mv) output (v) isl21440
10 fn6532.1 march 2, 2010 figure 15. hysteresis - 0mv (v+ = 3v) figure 16. hysteresis - 12.5mv (v+ = 3v) figure 17. hysteresis - 25mv (v+ = 3v) figure 18. hysteresis - 37.5mv (v+ = 3v) figure 19. hysteresis - 50mv (v+=3v) figure 20. output response time vs input overdrive (t phl ) typical performance curves (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output (v) -60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 in+ - in- (mv) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output (v) -60-55-50-45-40-35-30-25-20-15-10-5 0 5 1015202530354045505560 in+ - in- (mv) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output (v) -60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 in+ - in- (mv) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output (v) -60-55-50-45-40-35-30-25-20-15-10-5 0 5 1015202530354045505560 in+ - in- (mv) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 output (v) -60-55-50-45-40-35-30-25-20-15-10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 in+ - in- (mv) 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 100 110 120 input voltage (mv) time (s) 3v 5v isl21440
11 fn6532.1 march 2, 2010 functional description device power the isl21440 device has a sin gle positive supply pin, v+, and two other supply pins, v- and gnd. normally for single supply applicat ions the v- pin is tied to system ground as well as the gnd pi n. the separate ground pin allows the comparator to be powered by split supplies from 1.0v to 5.5v. note that the minimum supply voltage will be 0.8v above the comparator maximum input level for accurate operation. comparator section the comparator inputs can swing from the negative supply (gnd pin) to within 0.8v of the positive supply (v+). alternatively, with the comparator input set at the 1.182v reference level, the minimum input voltage for accurate operation is 2.0v. if the inputs are expected to see voltage levels above v+ or below ground, they should be clamped with low leakage schottky diodes. the cmos output swings essentially from the gnd potential to v+ potential, de pending on load current. if loads in excess of 1ma are expected, then a 0.1f decoupling capacitor at the v+ pin should be added. voltage reference section the voltage reference is a micropower fga reference and is set to 1.182v 0.5% at the factory. the reference output can source up to 2ma but the sink capability is very limited at only 10a, maximum. small value capacitors, up to 10nf, can be used on the reference output to lower noise if desired. applications information handling and board mounting fga references provide excellent initial accuracy and low temperature drift at th e expense of very little power drain. there are some precautions to take to insure this accuracy is not compromised. excessive heat during solder reflow can cause excessive initial accuracy drift, so th e recommended +260c max figure 21. output response time vs input overdrive (t plh ) figure 22. power-up/do wn output response (v+ = 5v, in+ = v+, in- = v ref ) figure 23. power-up/down output response (v+ = 3v, in+ = v+, in- = v ref ) typical performance curves (continued) 20 45 70 95 120 145 170 195 220 245 270 10 20 30 40 50 60 70 80 90 100 110 120 input voltage (mv) time (s) 3v 5v -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (ms) output (v) v+ out -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 v+ out time (ms) output (v) isl21440
12 fn6532.1 march 2, 2010 temperature profile should not be exceeded. expect up to 1mv drift from the solder reflow process. fga references are susceptible to excessive x-radiation like that used in pc board manufacturing. initial accuracy can change 10mv or more under extreme radiation. if an assembled board needs to be x-rayed, care should be taken to shield the fga reference device. hysteresis the hysteresis function allows for changing the value of the reference switchover point depending on the previouse state of the comparat or. this works to remove the effects of noise or glitches in the voltage detection input and provide more reliable output transitions. hysteresis is added to the isl21440 by connecting one resistor between the ref and hyst pins (r ref ), and another resistor(r hyst ) between the hyst pin and ground. the hysteresis voltage (v h ) is designed to be twice the voltage difference between the hyst pin and ref pin (v h = 2 * (v ref - v hyst )). since the reference voltage is 1.182v (v ref ), equations 1 and 2 for these two resistors are shown as follows: i ref is chosen to be less than the maximum output of the reference, usually 5a is a safe value but for lowest power, 0.1a can be used. if the hysteresis is not used, the hyst pin should be tied to the ref pin. board assembly considerations fga references provide high accuracy and low temperature drift but so me pc board assembly precautions are necessary. normal output voltage shifts of 100v to 1mv can be expect ed with pb-free reflow profiles or wave solder on multi-layer fr4 pc boards. precautions should be taken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures, this may reduce device initial accuracy. post-assembly x-ray inspection may also lead to permanent changes in device output voltage and should be minimized or avoided. if x-ray inspection is required, it is advisable to monitor the reference output voltage to verify excessive shift has not occurred. if large amounts of shift are observed, it is best to add an x-ray shield consisting of thin zinc (300m) sheeting to allow clear imaging, yet block x- ray energy that affects the fga reference. special applications considerations in addition to post-assembly examination, there are also other x-ray sources that may affect the fga reference long term accuracy. airport screening machines contain x-rays and will have a cumulative effect on the voltage reference output accuracy. carry-on luggage screening uses low level x-rays and is not a major source of output voltage shift, although if a product is expected to pass through that type of screening over 100x it may need to consider shielding with copper or aluminum. checked luggage x-rays are higher intensity and can cause output voltage shift in much fewer passes, so devices expected to go through those machines should definitely consider shielding. note that just two layers of 1/2 ounce copper planes will reduce the received dose by over 90%. the lead frame for the device which is on the bottom also provides similar shielding. if a device is expected to pass through luggage x-ray machines numerous times, it is advised to mount a 2-layer (minimum) pc boar d over the top of the package, which along with a ground plane underneath will effectively shield it from 50 to 100 passes through the machine. since these machines vary in x-ray dose delivered, it is difficult to produce an accurate maximum pass recommendation. typical applications low battery detector figure 24 shows a typical implementation for the isl21440, a low battery detector. the values for r ref and r hyst provide 20mv of hysteresis and 0.5a i ref . the input trip point for v detect is the same as the reference voltage, 1.182v, and a resistor divider at the input sets the lo bat trip point at 2.7v. the total current draw for the circuit is going to be 1.1a for v dd and 0.6a for v bat . r ref v h 2 ? i ref () ? v ref v hyst ? () i ref ? == (eq. 1) r hyst 1.182 v h ? 2 ? () i ref ? v hyst i ref ? == (eq. 2) v+ out in- hyst gnd v- ref in+ isl21440 - + v bat v dd 2.4m 20k lo bat - 2.4m 1.8m figure 24. low battery detector with hysteresis isl21440
13 fn6532.1 march 2, 2010 window comparator the isl21440 can be combined with a micropower to produce a window comparator circuit. the circuit in figure 25 uses a 3 resistor divider to produce high and low trip points, and the isl28197 (800na supply current) comparator is added to give the second output. the two outputs can be used separately for over or undervoltage indication, or a gate can be added as shown to report either in-window or out-of window condition. the resistors are shown as equations 3, 4 and 5 as follows. set: example: for v h = 3.8v, v l = 2.7v (3.3v 0.5v) r 2 = 402k, r 1 = 1.82m (can be 1%) the resulting circuit draws about 3a and works down to v dd = 2.2v. products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl21440 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php r 3 1m 1% () = (eq. 3) r 2 r 3 v h v l 1 ? ? [] = (eq. 4) r 1 r 3 v h v ref 1 ? ? [] r 2 ? () = (eq. 5) - + v+ out in- hyst gnd v- ref in+ isl21440 - + v bat r3 r1 r2 v low - v hi - v window isl28197 v bat or v dd figure 25. window comparator circuit revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 3/2/10 fn6532.1 updated datasheet with the tdfn spec. spec added on pages 5-6 are: vos, iin, cmrr and psrr. each spec has an added row for the tdfn package and the original limit for the msop package. 12/7/09 fn6532.0 initial release isl21440
14 fn6532.1 march 2, 2010 isl21440 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03
15 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6532.1 march 2, 2010 for additional products, see www.intersil.com/product_tree isl21440 package outline drawing l8.3x3g 8 lead thin dual flat no-lead plastic package (tdfn) rev 0, 5/07 c bottom view top view side view detail ?x? typical recommended land pattern 3.00 pin 1 index area (1.75) (1.45) (8x 0.25) (8x 0.60) (6x 0.50 bsc) see detail x'' 0.20 ref 0~0.05 5 pin 1 index area 8x 0.25 6x 0.50 bsc 1.75 1.50 ref 3.00 0.75 (2.20) 8x 0.40 2.20 4x a b 0.10 c a b 0.10 c seating plane 0.08 c c 1.45 notes: 1. controlling dimensions are in mm. dimensions in ( ) for reference only. 2. unless otherwise specified, tolerance : decimal 0.05 angular 2 3. dimensioning and tolerancing conform to jedec std mo220-d. 4. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 5. tiebar shown (if present) is a non-functional feature. 0.075 c m

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